- AMD’s 2nm “Venice” processor is the first implementation of TSMC’s N2 process.
- Company strengthens US manufacturing, producing EPYC processors at TSMC’s Arizona facility.
AMD’s 2nm chip breakthrough represents a defining moment in semiconductor advances. On April 14 the company announced that its forthcoming “Venice” processor is the first high-performance computing solution that’s been manufactured using 2nm technology. The achievement positions AMD and TMSC at the forefront of semiconductor miniaturisation, enabling greater computational power in significantly smaller chip designs and providing the AMD with a competitive advantage against long-time rival, Intel.
The next-generation AMD EPYC processor, code-named “Venice,” is the first high-performance computing (HPC) product to complete tape-out and bring-up phases on TSMC’s 2nm (N2) manufacturing process.
“Tape-out” signals the completion of the design phase before production, while “bring-up” confirms the processor has successfully initialised and passed preliminary validation tests – both important early checkpoints in processor development.
AMD’s 2nm chip breakthrough
The development underscores AMD’s productive partnership with TSMC, the world’s main semiconductor manufacturer. According to AMD’s official statement, the Venice processor remains on schedule for a 2026 launch.
The Venice processor uses TSMC’s N2 process, which implements gate-all-around (GAA) nanosheet transistor architecture – a departure from traditional designs. Technical specifications disclosed in the announcement reveal that TSMC’s N2 technology delivers either a 24-35% reduction in power consumption or a 15% performance enhancement at higher voltage levels. The company claims a 1.15x improvement in transistor density compared to the previous N3 generation.
Lisa Su, chair and CEO of AMD said, “Being a lead HPC customer for TSMC’s N2 process and TSMC Arizona Fab 21 are great examples of how we are working closely together […].”
The Venice architecture and TSMC’s advanced N2 process
Industry analysts anticipate the Venice processor will incorporate AMD’s Zen 6 micro-architecture using core complex dies (CCDs) in a modular architecture.
At the same time as the 2nm breakthrough, AMD has announced the validation of the 5th Generation EPYC CPU produced at TSMC’s new manufacturing facility in Arizona, as the company’s production in the US ramps up.
US manufacturing expansion and competitive implications
AMD’s announcement follows Intel’s disclosure of delays affecting its next-generation Xeon “Clearwater Forest” processor based on 18A manufacturing technology, which was developed to compete with TSMC’s N2. Intel has rescheduled the release of Clearwater Forest to the first half of next year, potentially providing AMD with a important time-to-market advantage.
Industry observers note that securing priority access to TSMC’s N2 process demonstrates AMD’s increasing value as a TSMC customer.
AMD’s ability to produce EPYC processors in the United States addresses concerns surrounding supply chain security for the US, and aligns with broader industry and governmental initiatives to strengthen domestic semiconductor production. The N2 process technology’s considerable reduction in power consumption could prove especially valuable for large-scale computing operations confronting rising energy costs and sustainability requirements.
The high-performance computing environment continues to transform, with AMD, Intel, and emerging ARM-based server processors competing for market share. The 2nm breakthrough provides compelling evidence that AMD intends to maintain aggressive x86 development timelines to build on recent market share gains in the profitable data centre segment.
